Blog Topics

Industry

1. The Structure of Industry – I
2. DFT vs DV (Design for Test vs Verification)

Clocks and Resets

1. Clock Gating
2. What is a Reset?
3. Lockup Latch
4. Reset Synchronizer

Timing

1. Setup and Hold Time
2. Timing Verification – I : Introduction to Static Timing Analysis
3. Timing Verification – II : Timing Paths
4. Timing Verification – III : Examples of setup/hold violation and How to fix
5. False Paths
6. Multicycle Paths

DFT – Design for Test

1. DFT – Fault Models
2. ATPG : Stuck-at and At-speed
3. Wrapper Chains
4. Scan and Resets
5. Scan Compression
6. Test Points
7. Boundary Scan/ JTAG – I
8. Boundary Scan/ JTAG – II
9. Boundary Scan/ JTAG – III (Boundary Scan Registers)

Storage / Memories

1. ROM
2. E-Fuse Based Memories – OTP

Communication Protocols

1. Serial Peripheral Interface – SPI
2. Inter Integrated Circuit – I2C
3. Advanced High-Performance Bus – AHB
4. Universal Asynchronous Receiver Transmitter-UART

Verilog

1. 4-Bit Up Counter
2. Synchronous FIFO
3. Verilog Constants – parameter, `define, localparam

Book Reviews

1. Microchip World – Ettore Accenti