Boundary Scan/JTAG – I

A PCB (Printed Circuit Board) assembles a number of Integrated circuits and other electrical components. When such an assembly is created, testing the integration is also necessary. As the density of such boards increased and further miniaturisation happened, it became impossible to access all the nodes with physical probes. Hence, the boundary scan testing technique was implemented many years ago and is still used extensively in almost all designs.

What is Boundary Scan?

Boundary scan refers to the additional test structure which acts as an interface between the outside of the chip and the inside logic. There is a cell (called Boundary Scan Cell) attached to each pin of the chip, which allows driving test values all over the boundary of the design and can take complete control of the pin/port. The purpose of this testing structure is to be able to test interconnections between different devices on the board.

A boundary scan cell has a structure shown in Figure 1. There are 4 possible directions of the signal flow in a BS cell, which are as follows:

1. From the port to the core (or core to the port) : This is a transparent mode where the BS cell allows the signal to pass in the same way as that in functional mode. The value passes through the BS cell from/to the port to/from the core logic.
2. From the port to the BS cell : This is a capture mode where the value at the port is captured inside a BS cell. The same mode is used to capture the value from core logic into the output BS cell.
3. From BS cell to the design logic : This is an update mode where a particular value stored in a BS cell can be propagated to the logic connected to BS cell (instead of the functional value directly from the port). Similarly, the outport ports can be driven by a stored value using this mode.
4. From previous BS cell to next BS cell : This is the shift mode where the test data is serially shifted from one BS cell to another.

The boundary scan cells for input, output or bidirectional ports are handled separately. We will discuss the actual design of boundary scan cell in further articles, where the select signals will also be explained.

How the interconnections are actually tested?

As shown in Figure 2, assume each port has a BS cell connected to it. The requirement is to test the interconnection 1,2,3,4,5 and 6. A combination of shift, update and capture procedures implement the testing. The process will be as follows in simpler words:

1. Serially shift in test values in BS cells of Device A.
2. Update the value being shifted to BS cell of Device A to its output ports.
3. Capture the values from input ports of Device B into respective BS cells.
4. Shift out the captured values from the BS cells of Device B to read them.

If the values read out from the shift-out pin of Device B are as expected, the interconnects are OK. If not, the faults need to be debugged further.

The above testing structure is called Boundary Scan. To implement such testing, a group called JTAG was formed which uses a TAP (Test Access Port) to drive the BS cells and other logic in the design. This was adopted as IEEE standard and is being used even today. The term JTAG and Boundary scan are used interchangeably as complete boundary scan testing is done through JTAG.

The TAP uses the combination of 4 pins: TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data-In) and TDO (Test Data-Out). There is an additional pin called TRST which is optional. These pins work together with a TAP controller, an Instruction Register (IR) and a Bypass register, to implement Boundary Scan testing. JTAG boundary scan testing structure is shown in Figure 3.

Along with Boundary scan testing, JTAG offers many more capabilities. It allows us to access the internal logic, used for implementing MBIST/LBIST, programming memories etc. and also offers many debugging features. We will eventually discuss the details in further articles.