Category: Verilog
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Verilog Constants
Parameter : While coding a Verilog module, there can be a constant value that needs to be used multiple times within the module. Such constants can be declared using ‘parameter’. Advantage : The biggest advantage of using ‘parameters’ is that, the code is scalable. A change in parameter value can be easily accommodated by the…
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Synchronous FIFO
FIFO is an important structure where data is stored and received in ‘First In First Out’ format. Consider an example of students entering a classroom by gate ‘A’ in line, and exiting through gate ‘B’ in the same line. The first student who entered will be the first one to exit the class. This format…
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4 Bit Up-Counter
When we talk about digital design, the language we use are HDLs (Hardware Description Language). Verilog is one such language which is used to create most of the designs. To get started with Verilog, lets study a simple 4 bit up-counter. Function: This counter is a 4 bit counter, i.e. it can count up to…
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