DFT vs DV

DFT – Design for Test

1. Checks structural faults : faults which may arise due to fabrication. Example: stuck at 0/1 faults, bridge faults. You can check DFT Fault Models to learn about other faults.
2. Term used for issues: FAULTS

DV – Design Verification

1. Checks functional faults : faults which may arise due to missing/wrong RTL code, or incorrect synthesis of code. This leads to incorrect functionality of design.
2. Term used for issues: BUGS

Sum ‘S’ = A xor B

Carry ‘C’ = A and B

DFT – Design for Test

Following is the gate-level representation of Half-adder with possible stuck-at faults in the circuit.

Lets suppose ‘B’ is stuck-at 0. The output obtained after running test patterns for this faulted design will be calculated based on following table:

A	B (Stuck-at 0)	S	C
0	0	0	0
0	1	0 Error	0
1	0	1	0
1	1	1 Error	0 Error

Why this was not detected during DV?

It is simply because the issue occurred after DV was done. The design was taped-out and went for fabrication. Stuck-at 0 fault at B occurred during manufacturing.

After the fabricated chip is run with the DFT test patterns, the test pattern output will not be as expected due to the above stuck-at fault. Further diagnosis will be done by analyzing the expected output and actual output to identify the exact fault.

DFT Skills required?

Being a DFT engineer does not require you to understand the function of the chip. The major skill is to be able to generate effective patterns (using DFT tools) and analyze them before and after fabrication, to identify faults.

However knowledge of Verilog is essential. DFT is inserted and integrated in the design at RTL level as well and DFT engineer’s job is not limited to patterns. Development/Integration/Maintenance of DFT related blocks in the design as well as guiding RTL designers to adopt good DFT practices while coding their blocks is also required of a good DFT engineer.

DFT Test Coverage

Test coverage in DFT is how many faults can the test-patterns cover. If coverage is 90%, it means 90% faults in the design can be detected by given patterns. To detect more faults in the design, patterns need to be improved.

Getting 100% test coverage in DFT is a challenging objective. Managing 99% stuck-at coverage and 90% transition fault coverage meets the purpose.

DV – Design Verification

If the RTL code is written with a mistake, and an OR gate is added instead of AND gate, the circuit will be as follows:

always@(*) begin

S = A ^ B;

C = A | B;

end

A	B	S = A xor B	C= A or B
0	0	0	0
0	1	1	1 Error
1	0	1	1 Error
1	1	0	1

Why this will not be detected in DFT?

Because DFT does not check if the intended functionality of design is correct.

If DV fails to detect this issue, DFT will generate patterns according to the wrong design (OR gate instead of AND gate). If there will be no manufacturing defects, DFT patterns will still pass. This will be possibly detected in further functional validation tests, which is out of scope for this article.

DV Skills required?

Being a Design Verification engineer revolves around how well you understand the intended functionality of design.

Based on how well a verification engineer understands the design specifications (created by RTL designers), he/she develops a set of features and corner cases. Then, testcases are developed to check them. RTL designers perform a first-level basic verification on their side, but the DV engineer is responsible for comprehensive tests so that no bug escapes. Verilog skills are extremely essential for the role, along with knowledge of System Verilog and UVM.

DV Test Coverage

Test coverage in DV is either functional coverage or code coverage.

Functional coverage : This defines how many features have been covered (based on a pre-defined set of functional features and corner case conditions).

Code coverage: This type of coverage measures how much of the code is tested via a given number of testcases.