False Path

While setting up timing constraints for different paths in the design, there are some paths which need special attention. The timing needs to be relaxed, and hence these are called Timing Exceptions. One such exception is ‘False paths’, which is discussed here.

Generally, a launch flop transmits a signal, which needs to be captured in the next clock cycle by the capture flop. But there are some paths along which, a transmitted signal can reach the other flop at any time (not just one clock cycle). These paths do not need any time constraint setting, and are termed as ‘false paths’.

One of the most common and important false path scenario is a 2-flop synchronizer, as shown in Figure 1.

In the figure 1, FF1  is in a different clock domain while FF2 and FF3 are in a different clock domain. If a signal is launched by FF1 and reaches FF2, the signal is considered to have crossed clock domains. (CDC-Clock domain crossing is a huge topic which will be discussed in a different article).

Since FF1 and FF2 are in different clock domains, there is high probability of setup/hold violation for FF2. Even if FF2 output is metastable (for less than 1 clock period), FF3 will avoid the metastable data and give a fixed output. This new value will be reflected once the metastable state is over. This metastability probability depends on the frequency of both the clocks. This type of 2-flop structure is basically used for synchronizing signals from 2 clock domains. So, timing is not needed from FF1 to FF2 (front stage of synchronizer) and it can be referred as ‘False path’.

Other False Path Scenarios:

The physical paths in the design which cannot be exercised are also termed as false paths. For example, the mux structure in Figure 2.

• When sel = 0, delay = 15 + 30 = 45 ns
• When sel = 1, delay = 30 + 15 = 45 ns
• There is no path through the buffers with delay 15+15 ns and 30+30 ns (false paths)
• Maximum topological delay is 30+30 ns, but maximum functional delay is 15+30ns.

One such false path scenario is show in Figure 3.

• If D2.Q=0 => D4.D=0
• If D2.Q=1 => D4.D=1
• There is no effect of value of D1.Q on D4.D. So, the path D1.Q to D4.D is a false path.