Timing verification – III

• Tcq = 0.1ns = 100ps
• Tcomb = 0.9ns = 900ps
• Tperiod = 1ns
• Tsetup = 0.1ns = 100ps
• Tskew = 0.15ns = 150ps
• Tuncertainty = 0.25ns = 250ps

• Tcq = 30ps
• Tcomb = 40ps
• Tskew = 70ps
• Thold = 10ps

Setup

General Equation:

Tc-q + Tcomb < Tperiod – Tsetup + Tskew

Improve the driving strength of the Launch flip-flop. Higher the driving strength, faster the charging/discharging of gate capacitances and hence, lesser the combinational delay.

Use a flip-flop with less Tc-q.

Use logic restructuring techniques to change the combinational logic to be optimized to have a smaller delay paths.

Use the flop with less Tsetup (low setup time constraint).

Use an LVT (low threshold voltage) cells instead of SVT and HVT (standard and high threshold voltage) cells, as it takes less time for switching, and hence makes the flop faster.

Increase the skew to relax setup timing. (as per the equation mentioned above)

If there is no change possible in the design, increase the clock period. The setup violation will go based on the given equation.

Hold

General Equation:

Tc-q + Tcomb > Thold + Tskew

Decrease the driving strength of launch flip-flop. Lower the driving strength, slower the charging/discharging of gate capacitances and hence, higher the combinational delay.

Use a flip-flop with more Tc-q.

Add buffers in the data path to increase the combinational delay, to ease the hold timing.

Use the flop with less Thold (low hold time constraint)

Use a HVT (high threshold voltage) cells instead of LVT and SVT (low and standard threshold voltage) cells, as it takes more time for switching, and hence, introduces more delay.

Decrease the skew to ease hold timing. (as per the equation mentioned above)

If you cant really make any change, reduce the operating voltage. It might help fixing the hold violation.