Category: Timing

This is the most common concept studied in VLSI, and hence most important. We tend to understand the definition but the concept creates confusion at times. Let us revisit this topic in simple terms. Setup Time The time before the active clock edge, when the data signal is not allowed to change its value Hold…

Multicycle paths are another kind of timing exception like false paths. Generally, data launched from one flop reaches the next flop in one clock cycle. But there may be cases where it takes more than one clock cycle to reach the destination flop. Such paths are termed as ‘Multicycle paths’. This can be due to…

While setting up timing constraints for different paths in the design, there are some paths which need special attention. The timing needs to be relaxed, and hence these are called Timing Exceptions. One such exception is ‘False paths’, which is discussed here. Generally, a launch flop transmits a signal, which needs to be captured in…

Timing Paths The basics of timing verification have been covered in the article ‘Timing verification – I‘. Please go through ‘setup and hold time‘ to refresh your concepts. This article will focus on the timing paths. There are four kinds of timing paths that can be found in a design: Primary input to the data…

Introduction to STA There are certain timing specifications associated with the design, which are tested during ‘timing verification’. Timing is an integral part of chip designing and it basically separates a hardware and software code. It also determines the maximum frequency at which a design can operate. Functional verification does not consider propagation delays and…