Category: Clocks and Resets
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Lockup Latch
There are a number of clock domains in modern day’s complex SoCs. When the flip-flops in such designs are stitched into scan chains, there is a possibility that there are two clock domains in one scan chain. This means that at one point in the scan-chain, the launch flop and capture flop will belong to…
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What is a RESET?
You will come across RESETs even in simplest designs, making it one of the most important topic to discuss. Lets dive in….. A Reset is a signal which forces the design into a known state. This unique and important capability can be used to: Types of Reset: Synchronous Reset affects the flip-flop only at an…
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Clock Gating
Let us discuss clock gating in simplest terms. Definition: Technique to switch off the clock when not in use. It reduces the switching activity and hence, saves dynamic power, without affecting the design functionality. Simplest Clock Gating Naming: ‘en’: Enable signal. ‘clk’: The non-gated original cloc ‘g_clk’: Gated clock (off when not in use) Working:…
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Reset Synchronizer
Resets are one of the most critical signals in a design. ‘What is a reset?’ discusses all the basics about them. An issue with asynchronous reset was mentioned in this article, which is, de-assertion of asynchronous reset. If this de-assertion occurs close to an active clock edge, it violates the timing and causes metastability. There…
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