Communication Protocols – I2C

I2C stands for Inter Integrated Circuit, and is one of the most important communication protocol. It was developed by Philips semiconductor, which is now known as NXP semiconductors. Lets get to know how it works.

Inter-Integrated Circuit
Bidirectional, serial protocol
Synchronous communication (due to the clock line)
2-wire protocol (SCL – Serial Clock Line and SDA – Serial Data Line)
Supports 7-bit and 10 bit addressing
Master slave configuration (can support multiple masters and multiple slaves) -> Number of devices are limited by bus-capacitance.
Example: Master: controller, Slave: Memory
Different speed modes: standard <= 100 Kbit/s, fast mode <= 400 Kbit/s, fast mode plus <= 1 Mbit/s, high speed <= 3.4 Mbit/s, ultra-fast mode <= 5 Mbit/s

Figure 1

Open Drain Configuration:

The output stage of the devices connected to the i2c bus, must have ‘open-drain’. Open drain/collector is the configuration where an nMOS transistor has its source connected to the ground, base connected to the input, and drain is left open. This leads to two conditions:

When transistor is active => The value at ‘D’ is 0 (pulled down)
When transistor is inactive => The value is floating

This configuration is used along with a pull-up resistor, so that the value is pulled-up to ‘1’ whenever the transistor is inactive. Hence, in i2c bus, SDA can be pulled LOW from its HIGH (default/free) state to indicate the start of a transaction.

How the transfer works?

Step 1: The start stop condition is as follows:

SDA: 1-> 0 when SCL=1 => Start the transaction
SDA: 0 -> 1 when SCL=1 => Stop the transaction

Figure 3

Data on SDA should never change when SCL is ‘1’ except the above two conditions.
A master can only occupy the bus if it is IDLE. If the bus is BUSY (i.e. another transaction is going on), it has to wait until the bus is free again.
Hence, to start the transaction, SDA is pulled LOW when SCL is HIGH.

Step 2:

After the start condition, one bit transfer occurs over each clock cycle.
The data transfer occurs in byte format (1 Byte = 8 bits)
Each byte is acknowledged with an extra bit called as ACK/NACK bit.
The number of bytes that can be transferred is unrestricted.
If the target is not ready to send/receive the data, it holds SCL to LOW until it is ready. Data transfer continues when the target is ready as SCL is released. This feature is called ‘clock stretching‘.

Address Transfer:

Each device has a unique address.
After the START condition, the address is sent by the master to detect the target device. This also includes a bit (R/W) to indicate READ/WRITE operation.
There are two addressing modes: 7-bit addressing and 10 bit addressing, which will be discussed later.
The target devices sends an acknowledgement signal if the address is matched.

Data Transfer:

After the target device is located, it works according to READ/WRITE bit.

WRITE(R/W bit = 0)

The master continues to send bytes of data and receiver/slave sends an acknowledge bit after each byte transfer.

READ (R/W bit = 1)

The slave takes control of the bus and starts sending the bytes of data to the master. Now, master sends the acknowledge bit after each byte transfer.

Figure 4

Step 3: SDA is pulled HIGH when SCL is HIGH to indicate a STOP condition. The bus is released to be idle or free again.

Additional Important Points:

ACK/NACK Bit:

Whenever a byte is transferred over i2c, it is followed by an acknowledgement bit. The device which is receiving the data takes control of SDA and pulls it LOW during the 9th clock pulse. If it remains HIGH during this clock pulse, it indicates a NACK (NO- acknowledgement). In this case, master stops the transfer or the transfer is re-initiated.

Bus Arbitration:

If there are multiple Masters connected on the bus, there can be an ambiguity if both masters try to use the bus at the same time. So, i2c has a proper arbitration scheme for such cases. The Master who sends a ‘0’ first wins. Let us take an example below:

Figure 5

The transfer is seen from MSB (right to left here). First, Master 3 loses arbitration on sending ‘1’ when others are sending ‘0’. Secondly, Master 1 loses arbitration on sending a ‘1’ and Master 2 wins the arbitration.

Addressing Modes:

7 Bit Addressing: The address byte is 8 bits = 7 bit device address + 1 R/W bit.

10 Bit Addressing: After start condition, 2 bytes are sent.

First Byte: 1111 0XX(R/W) => The target device uses these first 7 bits to match with its own address, checks for R/W bit. More than 1 device might find a match and all of them send an acknowledgement bit. Then, these selected devices read the second byte “XXXX XXXX” to find the exact target device, which sends an acknowledgement again (total 2 acknowledgement bits are sent). OR

First Byte: 1111 1XX(R/W) => This combination of first byte is reserved for future i2c bus enhancements.

Cons of I2C:

Frame overhead due to ACK/NACK bits and device address, reduces the overall speed of transfer.
Half-duplex communication.
More complex hardware when more master/slave devices are added.